DRAMs are composed of a multiplicity of memory cells which are formed regularly in the form of a matrix on a semiconductor wafer. Said memory cells generally comprise a storage capacitor and a selection transistor. During a read or write operation, the storage capacitor is charged or discharged, via the selection transistor, with an electrical charge corresponding to the respective data unit (Bit). For this purpose, the selection transistor is addressed with the aid of a bit line and a word line.
DRAMs are generally realized with the aid of planar technology. The latter comprises a sequence of individual processes which, in each case, act over the whole area at the surface of the semiconductor wafer and, by suitable masking layers, lead in a targeted manner to the local alteration of the semiconductor material. In this case, the selection transistor of the memory cell is generally embodied as a field-effect transistor, with two highly doped diffusion regions in the semiconductor wafer, which form the source/drain electrodes. A channel is formed between these two diffusion regions, via which channel an electrically conductive connection can be produced with the aid of a gate electrode formed above the channel. In the case of DRAMs, the gate electrodes of the field-effect transistors are realized as gate electrode tracks which run parallel and form the word lines of the DRAM. The bit lines then run transversely over said gate electrode tracks, a conductive connection between a bit line and a source/drain electrode of the selection transistor of a corresponding memory cell being produced in the interspace between two gate electrode tracks.
The bit line contact is usually fabricated as a so-called “self-aligned” contact in the DRAM process. A possible process sequence for forming such bit line contacts is illustrated diagrammatically in FIG. 4. FIGS. 4A to 4D respectively show a cross section through a silicon wafer after various successive process steps for forming the bit line contacts. The starting point is the prepatterned silicon wafer 1, on which gate electrode tracks 2 spaced apart equidistantly have been formed. These gate tracks 2 generally comprise a conductive layer stack 21 covered by a silicon nitride cap 22. Insulating spacers 23, preferably made of silicon nitride, are formed at the sidewalls of the gate electrode tracks 2. A cross section through the correspondingly prepatterned silicon wafer is shown in FIG. 4A.
A further silicon nitride layer 300 is deposited in a first step for forming the bit line contacts. In order to define the region of the bit line contacts on the silicon wafer 1, a mask layer sequence 350, 400 is subsequently produced, and completely covers the bit line contacts. FIG. 4B shows a cross section through the silicon wafer 1 after this process step.
With the aid of a lithography step, the regions at which the bit line contacts of the selection transistors are later intended to be produced are then defined on the mask layer sequence 350, 400. These regions of the mask layer sequence 350, 400 are then opened with the aid of a selective etching. By a further etching, the silicon nitride layer 300 is then removed in the opening regions of the mask layer sequence 350, 400. The resultant silicon wafer configuration is shown in FIG. 4C. During the silicon nitride etching, the silicon nitride layer 300 is etched away essentially only at the horizontal areas, but remains at the sidewalls of the gate electrode tracks 2, as is shown in FIG. 4C.
In a final process step, the contact openings are then filled with a conductive material in order to fabricate the bit line contacts 9. A cross section through the silicon wafer 1 after the production of the bit line contacts 9 is shown in FIG. 4D.
Such a standard process for producing bit line contacts is known inter alia from WO 01/09946. This standard process essentially has three significant disadvantages. The distance between two mutually adjacent gate electrode tracks between which the bit line contact is intended to be embodied is additionally decreased by the silicon nitride spacers at the sidewalls of the gate electrode tracks. This gap narrowing increases the aspect ratio, that is to say, the ratio of width to height of the contact openings, as a result of which processes that are to be performed in the contact openings become increasingly more difficult. This problem is intensified from DRAM generation to DRAM generation on account of the ever smaller lateral dimensions. Furthermore, owing to its high dielectric constant, the silicon nitride spacer in the contact hole leads to a strong coupling between the conductive material in the bit line contact and the gate electrode tracks, so that there is the risk of the electrical properties of the memory cells being impaired. The use of silicon nitride as a spacer for forming the bit line contacts has the disadvantage, moreover, that, on account of the directional etching required, an etching process with a high sputtering element is required, it being possible for the gate electrode tracks to be attacked and damaged particularly in the upper edge region.